1. Field of the Invention
This invention relates generally to clock receivers, and more specifically to an AC-coupled clock receiver for receiving a single-ended clock signal.
2. Related Art
FIG. 1 is a schematic diagram of a prior art clock receiver 101. An external reference clock generator provides a clock signal to an external clock input node 102. There is a capacitor 106 between the external clock input node 102 and a first node 103 of the clock receiver 101 for coupling alternating current (“AC”) of the clock signal to the first node 103. The clock signal is a single-ended clock signal and may be one of several voltages higher than the operating voltage of the clock receiver 101. A phase-locked loop control logic supplies a 3-bit receiver select signal 107 to a receiver select input node 104. The clock receiver 101 comprises a first programmable transistor 111, a second programmable transistor 112, and a third programmable transistor 113. The programmable transistors are NMOS transistors. The source of each programmable transistor is coupled to ground, and the gate of each programmable transistor is coupled to a 1-bit receiver select line 115, 116 and 117 that is coupled to the receiver select input node 104 through a buffer 105. The clock receiver 101 comprises a first protection capacitor 121, a second protection capacitor 122, and a third protection capacitor 123. Each protection capacitor is coupled between the first node 103 and the drain of the first programmable transistor 111, the second programmable transistor 112, and the third programmable transistor 113, respectively. One embodiment of the prior art clock receiver 101 also comprises a first diode 131 coupled between the first node 103 and VDD, and a second diode 132 coupled between the first node and ground. The diodes 131 and 132 may perform a clamping operation during power-up. The clock receiver 101 further comprises an inverter 140 that has an input coupled to the first node 103 and an output coupled to an output buffer 150. The output buffer 150 is coupled to an output node 151. The inverter 140 comprises a PMOS transistor 141 and a NMOS transistor 142.
The clock receiver 101 includes a first state-dependent resistive transistor 161 having a drain coupled to the first node 103, a gate coupled to the output of the inverter 140 and a source coupled to VDD. The first state-dependent resistive transistor 161 is a PMOS transistor. The clock receiver 101 also includes a second state-dependent resistive transistor 162 having a drain coupled to the first node 103, a gate coupled to the output of the inverter 140 and a source coupled to ground. The second state-dependent resistive transistor 162 is a NMOS transistor. The purpose of the state-dependent resistive transistors 161 and 162 is to drive the input of the inverter all the way to ground or all the way to VDD. When the signal at the output of the inverter goes from high to low, the first state-dependent resistive transistor turns on, and causes the DC signal at the input to the inverter to be at VDD. When the signal at the output of the inverter goes from low to high, the second state-dependent resistive transistor turns on, and causes the DC signal at the input to the inverter to be at ground.
The input capacitor 106 and the protection capacitors 121, 122 and 123 form a programmable AC voltage divider that divides the clock signal into an appropriate voltage swing so that the gates of inverter transistors 141 and 142, and the gates of the state-dependent resistive transistors 161 and 162, in regular VDD domain, can receive the clock signal without breaking a reliability requirement. The receiver select signal 107 is set to an appropriate value to determine a correct divider ratio of the programmable AC voltage divider. The value of the receiver select signal 107 depends on the voltage of the clock signal provided by the external reference clock generator. The receiver select signal 107 selectively applies a voltage to the gate of one or more of the programmable transistors 111, 112 and 113 via 1-bit receiver select lines 115, 116 and 117.
If the operating voltage of the clock receiver 101 is 1V, the threshold, or trip point, of the inverter 140 is generally 0.5V, or VDD/2. The external reference clock generator provides a 3.3V single-ended clock signal, which means that the clock signal varies between 3.3V and 0V. When the external reference clock generator provides a 3.3V clock signal, the PLL control logic provides a receiver select signal 107 whose value causes the AC voltage divider of the clock receiver 101 to divide the 3.3V clock signal from the external reference clock generator by approximately three (3), thereby producing a signal that varies between approximately 1V and 0V at the first node 103. However, if, for any reason, the clock signal is degraded externally to the clock receiver 101, for example, from 3.3V to 1V then, after the 1V signal is divided by approximately three (3) by the AC voltage divider of the clock receiver 101, a signal that varies between approximately 0.3V and 0V is produced at the first node 103. However, the inverter 140 is expecting 1V peak-to-peak signal. Therefore, the 0.3V signal is not enough to reach the threshold, or trip point, of the inverter 140. Furthermore, the state-dependent resistive transistors 161 and 162 drive the signal at the input to the inverter 140 to either 1V DC or to 0V DC. Therefore, when the 0.3V peak-to-peak alternating voltage signal resulting from the received, divided clock signal is combined with 1.0V DC, the closest the voltage at the input to the inverter 140 can come to the trip point is 1.0V−0.3V=0.7V. And, therefore, when the 0.3V peak-to-peak alternating voltage signal resulting from the received, divided clock signal is combined with 0V DC, the closest the voltage at the input to the inverter 140 can come to the trip point is 0V+0.3V=0.3V. In neither case, does the voltage at the input to the inverter 140 reach the 0.5V threshold of the inverter; therefore, the inverter fails to work. Consequently, the receiver 101 fails to work.
Another way of describing the foregoing disadvantage of the prior art clock receiver 101 is as follows. In theory, the clock receiver 101 will fail when a voltage input high of a nominal 3.3V clock signal from a 3.3V domain external reference clock generator degrades below 1.5V. In practice, the clock receiver 101 will likely fail before the voltage degradation of the nominal 3.3V clock signal from the 3.3V domain external reference clock generator reaches 1.65V.
The clock receiver 101 may receive a clock signal from multiple voltage domains and the clock signal may be on before all power domains are stable. If the clock receiver 101 is receiving the clock signal from a higher voltage domain than that of the clock receiver 101, and if the clock receiver has not finished powering-up, the clock receiver can be damaged. Within a voltage domain, a voltage swing variation of the clock signal and/or a variation of the trip point of the inverter 140 can distort the duty cycle of the received clock signal, and may permanently damage of the clock receiver 101. Some other known prior art receivers use a pair of diode-connected PMOS transistors by itself, or a pair of diode-connected NMOS transistors by itself; in either case, such a pair always sets the common mode to VDD/2. However, these other known prior art receivers do not fully compensate for voltage swing variations within a voltage domain.
The “common mode” of a signal, such as the clock signal, refers to a DC voltage level of the signal, or may refer to an average between a voltage input high (VIH) and a voltage input low (VIL) of the signal. In the prior art receiver 101 of FIG. 1, the common mode of the signal at the input of the inverter 140 does not track the trip point of the inverter.